With regard to a receiver incorporated in a semiconductor integrated circuit for processing radio frequency (RF) signals in a mobile terminal for wireless communication or the like, it is commonly known to those skilled in the art that a superheterodyne scheme or a direct conversion scheme is used as a method for frequency conversion from the RF band to the baseband (low frequency band). In the superheterodyne scheme, received signals are frequency-converted through plural-step down-conversion processes; from the RF band to the intermediate frequency (IF) band, and then from the IF band to the baseband. Contrastingly, in the direct conversion scheme, received signals are frequency-converted through a single-step down-conversion process from the RF band directly to the baseband.
As compared with the superheterodyne scheme that uses the IF band, the direct conversion scheme is advantageous in that the physical size of a receiver can be reduced since IF-band-related circuit/filter components are not required. Hence, the direct conversion scheme is currently in widespread use for such a circuit as a radio frequency integrated circuit (RFIC) incorporated in a mobile terminal. The direct conversion scheme is, however, disadvantageous in that signal degradation is likely to occur due to flicker noise or DC component fluctuations (DC offset) caused by self-mixing. The term “flicker noise” as used herein signifies a kind of noise that appears in the vicinity of DC and increases in inverse proportion to frequency. The signal degradation due to DC offset is problematic particularly in the direct conversion scheme, though not limited thereto. Further, there may arise a problem regarding a settlement time period of a transient signal that occurs at the time of gain changeover in a baseband signal processing section used for processing baseband signals. For removing the DC offset, it is common practice to employ a highpass filter (HPF), which is designed for precluding a low frequency band. For preventing possible degradation of a desired signal appearing in a near-DC band, a cutoff frequency needs to be set up at a sufficiently low level in the highpass filter (HPF). In order to set up the cutoff frequency at a sufficiently low level, it is required to provide relatively large capacitance and resistance values in the design of the highpass filter (HPF). Since device elements having larger capacitance/resistance values are larger in physical size in general terms, the provision of the device elements having larger capacitance/resistance values will hinder reduction in physical size in the highpass filter (HPF) design. Further, in cases where device elements having larger capacitance/resistance values are included in the highpass filter (HPF), a time required for gain settlement is prolonged disadvantageously due to an increase in time constant of circuitry.
In Patent Document 1 indicated below, there is disclosed a technique wherein, for realizing high-speed operation in a direct-conversion transceiver, a cutoff frequency changeover is performed in a highpass filter (HPF) thereof while removing DC offset. More specifically, for a predetermined control time period to elapse from the start of RF signal reception, a higher cutoff frequency is set up by decreasing the time constant of the highpass filter (HPF) for shortening a settlement time. Thereafter, for a period corresponding to prevention of degradation of a desired signal, a lower cutoff frequency is set up by increasing the time constant thereof. Thus, it is intended to realize high-speed operation while removing DC offset.
Patent Document 1:
Japanese Unexamined Patent Publication No. 2005-286810